Multilevel Cache Hierarchy Simulator in C++

Implemented a 2-Level Cache Simulator in C++ to model caching behavior of several replacement policies (LRU, FIFO and PseudoLRU) and inclusion policies((Exclusive ,Inclusive and Non-exclusive and Non-inclusive) with Write‐Back Write Allocate (WBWA) policy.
Purpose: To estimate the cache miss rates for different cache configurations when running different workloads.This would help in choosing a particular cache hierarchy before designing the cache in hardware.

Branch Predictor Simulator in C++

Every code has If-else statements. How the processor core handles these branch instructions has a serious impact on the performance of the core. So, there are some branch predictors that help core handle branch instructions more efficiently.

Implemented various branch predictor simulators in C++ to model the predictors(Bimodal, Gshare, Hybrid, Yeh-Patt) used in hardware along with a Branch Target Buffer.

Purpose: To estimate the misprediction rates for different predictors when running different workloads. This would help in choosing a particular branch predictor before designing the branch predictor in hardware.

Principle of out-of-order processing is to allow independent younger instructions to execute before dependent older instructions and avoid stalling the entire pipeline. This is done by allowing the younger instruction to execute, but not allowing them to make any changes in the register files.

Simulated a configurable Out of order superscalar processor of a 9-stage pipeline(consisting of instruction fetch, decode, rename, register read, dispatch, issue, execute, write-back and retire stages) in C++. The simulator fetches and issues N instructions per cycle.

Pupose: In a processor design, there is always a trade-off in terms of cost of hardware vs. performance. By changing the parameters to the processor simulator, we can find out the hardware cost for the required throughput before designing the actual hardware on silicon.